Data storage in high-density memory devices may be accomplished using a variety of techniques. Often, the technique used depends upon whether or not the stored data is volatile or non-volatile. In volatile memory devices, such as SRAM and DRAM, for example, stored data may not be retained when power is removed from the memory device. On the other hand, for non-volatile memory devices, such as MRAM and FLASH devices, stored data may be retained when power is removed from the memory device.
Non-volatile memory devices having a memory cell including an electrolytic tunnel barrier layer in contact with an oxygen reservoir provided solutions for data retention, where the memory effect may be achieved during a program state when an electric field is applied across the electrolytic tunnel barrier layer. The electric field at the tunnel barrier is typically high enough to promote tunneling, and additionally, the electric field may penetrate the conductive oxide layer by at least a Debye length. When the polarity of a bias (voltage) applied across the memory cell is sufficient to enable an electric field to effectuate the movement of ions, whether positively or negatively charged, ions from the oxygen reservoir may be transported to and from the electrolytic tunnel barrier layer. In turn, current flows through the memory element.
When this occurs, the resistive memory effect (RME) may be measured against the width (e.g., thickness) of the electrolytic tunnel barrier layer. In general, an electrolytic tunnel barrier layer fabricated to a thicker width is desirable in order to achieve a higher RME. It would also be desirable to be able to increase the thickness of the electrolytic tunnel barrier layer to a maximal value in order to maximize the RME. However, there are practical restrictions on tunnel barrier thickness. For example, of the tunnel barrier is too thick (e.g., approximately >50 Å), then the applied voltages necessary for tunneling may exceed the capability of circuitry (e.g., CMOS devices) employed in conventional integrated circuit memory devices to supply the voltages for data operations (e.g., read and write operations).
Additionally, it has been observed that when the thickness of the electrolytic tunnel barrier layer increases, the current enabled to flow through the memory cell generally decreases. This occurs because the increased thickness of the electrolytic tunnel barrier layer presents a higher conduction barrier for ions to overcome when the memory cell is biased. When the memory cell is biased, achieving a higher current flow is beneficial so as to achieve a higher RME. Accordingly, it would be desirable to increase the thickness of the electrolytic tunnel barrier layer and increase the current capable of flowing through the memory cell so as to achieve a high RME while keeping the thickness of the electrolytic tunnel barrier layer within a range that does not exceed the voltage capabilities of drive circuitry that supply the voltages for data operations.
There are continuing efforts to improve design of non-volatile memory devices.
Although the previous drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the FIGS. are not necessarily to scale.